
SV51008
2014.01.10
Figure 7-17: Delay Chains in the DQS Input Path
DQS
DQS delay
I/O and DQS Configuration Blocks
7-27
DQS
Enable
dqsin
chain
T7
delay
dqsbusout
chain
dqsenable
T11
delay
chain
DQS
Enable
Control
Related Information
Provides more information about programming the delay chains.
? DQS Delay Chain on page 7-20
I/O and DQS Configuration Blocks
The I/O and DQS configuration blocks are shift registers that you can use to dynamically change the settings
of various device configuration bits.
? The shift registers power-up low.
? Every I/O pin contains one I/O configuration register.
? Every DQS pin contains one DQS configuration block in addition to the I/O configuration register.
Figure 7-18: Configuration Block (I/O and DQS)
This figure shows the I/O configuration block and the DQS configuration block circuitry.
MSB
bit2
bit1
bit0
datain
update
ena
dataout
rankselectread
rankselectwrite
clk
Related Information
Provides details about the I/O and DQS configuration block bit sequence.
External Memory Interfaces in Stratix V Devices
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